Using Make for Compilation

This chapter describes the basic knowledge of make compilation and provides examples for demonstration. For more information about Make, run the man make command.

• Using Make for Compilation
  • Overview
  • Basics
    • File Type
    • make Work Process
    • make Options
  • Makefiles
    • Makefile Structure
    • Makefile Contents
  • Examples
    • Example of Using Makefile to Implement Compilation

Overview

The GNU make utility (usually abbreviated as make) is a tool for controlling the generation of executable files from source files. make automatically identifies which parts of the complex program have changed and need to be recompiled. Make uses configuration files called makefiles to control how programs are built.

Basics

File Type

Table 1 describes the file types that may be used in the makefiles file.

Table 1 File types

make Work Process

The process of deploying make to generate an executable file from the source code file is described as follows:

1. The make command reads the Makefiles, including the files named GNUmakefile, makefile, and Makefile in the current directory, the included makefile, and the rule files specified by the -f, --file, and --makefile options.
2. Initialize variables.
3. Derive implicit rules, analyze dependencies, and create a dependency chain.
4. Determine which targets need to be regenerated based on the dependency chain.
5. Run a command to generate the final file.

make Options

make command format: make [option]... [target]...

In the preceding command:

option : parameter option.

target : target specified in Makefile.

Table 2 describes the common make options.

Table 2 Common make options

Makefiles

Make is a tool that uses makefiles for compilation, linking, installation, and cleanup, so as to generate executable files and other related files from source code files. Therefore, makefiles describe the compilation and linking rules of the entire project, including which files need to be compiled, which files do not need to be compiled, which files need to be compiled first, which files need to be compiled later, and which files need to be rebuilt. The makefiles automate project compilation. You do not need to manually enter a large number of source files and parameters each time.

This chapter describes the structure and main contents of makefiles. For more information about makefiles, run the info make command.

Makefile Structure

The makefile file structure is as follows:

targets:prerequisites

command

or

targets:prerequisites;command

command

In the preceding information:

• targets : targets, which can be target files, executable files, or tags.
• prerequisites : dependency files, which are the files or targets required for generating the targets. There can be multiple or none of them.
• command : command (any shell command) to be executed by make. Multiple commands are allowed, and each command occupies a line.
• Use colons (:) to separate the target files from the dependency files. Press Tab at the beginning of each command line.

The makefile file structure indicates the output target, the object on which the output target depends, and the command to be executed for generating the target.

Makefile Contents

A makefile file consists of the following contents:

• Explicit rule

  Specify the dependency, such as the file to be generated, dependency file, and generated command.

• Implicit rule

  Specify the rule that is automatically derived by make. The make command supports the automatic derivation function.

• Variable definition

• File indicator

  The file indicator consists of three parts:

  • Inclusion of other makefiles, for example, include xx.md
  • Selective execution, for example, #ifdef
  • Definition of multiple command lines, for example, define...endef. (define ... endef)

• Comment

  The comment starts with a number sign (#).

Examples

Example of Using Makefile to Implement Compilation

1. Run the cd command to go to the code directory. The ~/code directory is used as an example.

   cd ~/code
   

2. Create a header file hello.h and two functions hello.c and main.c.

   vi hello.h
   vi hello.c
   vi main.c
   

   The following is an example of the hello.h code:

   #pragma once
   #include <stdio.h>
   void hello();
   

   The following is an example of the hello.c code:

   #include "hello.h"
   void hello()
   {
           int i=1;
           while(i<5)
           {
                   printf("The %dth say hello.\n", i);
                   i++;
           }
   }
   

   The following is an example of the main.c code:

   #include "hello.h"
   #include <stdio.h>
   int main()
   {
           hello();
           return 0;
   }
   

3. Create the makefile.

   vi Makefile
   

   The following provides an example of the makefile content:

   main:main.o hello.o
           gcc -o main main.o hello.o
   main.o:main.c
           gcc -c main.c
   hello.o:hello.c
           gcc -c hello.c
   clean:
           rm -f hello.o main.o main
   

4. Run the make command.

   make
   

   After the command is executed, the commands executed in makefile are printed. If you do not need to print the information, add the -s option to the make command.

   gcc -c main.c
   gcc -c hello.c
   gcc -o main main.o hello.o
   

5. Execute the ./main target.

   ./main
   

   After the command is executed, the following information is displayed:

   The 1th say hello.

   The 2th say hello.

   The 3th say hello.

   The 4th say hello.